The present disclosure relates to a time-to-digital converter which converts a time difference between edges of two input signals to a digital value.
In recent years, as the miniaturization of LSIs progresses, the operating voltage of LSIs is lowered. Therefore, it has been difficult to improve the SN ratio of a signal in signal processing in the voltage direction. Therefore, under the necessity of performing signal processing using analog quantity in the time direction, i.e., time difference information, in recent years, a time-to-digital converter which converts a time difference between edges of two input signals to a digital value has been developed. For example, see Jinn-Shyan Wang, Yi-Ming Wang, Chin-Hao Chen, Yu-Chia Liu, “An Ultra-Low-Power Fast-Lock-in Small-Jitter All-Digital DLL”, ISSCC 2005/SESSION 22/PLL, DLL, AND VCOs/22.7, 2005 IEEE International Solid-State Circuit Conference, pp. 422-423 and 607.
A known time-to-digital converter realizes addition and subtraction of the time difference by delaying one of the two input signals by a delay circuit. However, the delay circuit has a large delay error, and therefore, it is difficult to improve conversion accuracy using a known method. As described above, the conversion accuracy of time-to-digital converters which have been developed up until today is not sufficient, and there is the need for the development of a time-to-digital converter which can generate highly accurate digital time-difference information that is to be a reference for each of various electronic devices.
As described above, there is a need for an oversampling time-to-digital converter which can convert time-difference information to a digital value with high accuracy.